1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage device. More particularly, it relates to an electrically erasable programmable read only memory (EEPROM) in which data can be electrically rewritten.
2. Description of the Related Art
As is well known, there are roughly two kinds of transistor elements in an EEPROM. One is a transistor element (hereinafter, a cell transistor) provided in a memory cell unit. The cell transistor has a gate electrode structure in which a tunnel oxide film, a floating gate electrode, an interpoly insulating film and a control gate electrode are stacked from bottom to top in this order on a substrate. This cell transistor keeps data nonvolatile by a difference of a threshold value which changes depending on whether or not the floating gate electrode is charged. The other transistor element is a peripheral transistor provided in a peripheral circuit unit. The peripheral transistor has the same gate electrode structure as that of the cell transistor except for the interpoly insulating film. That is, the peripheral transistor has a metal insulator semiconductor field effect transistor (MISFET) structure in which the interpoly insulating film is partly or entirely opened so that a control gate electrode is electrically connected to a floating gate electrode. Moreover, the peripheral transistor is classified into two kinds of peripheral transistors having a thick gate oxide film and a thin gate oxide film, depending on the level of drive voltages. A peripheral transistor having a thick gate oxide film is called a high voltage transistor, while a peripheral transistor having a thin gate oxide film is called a low voltage transistor. This peripheral transistor is mainly used to construct a logic circuit.
In the case of the EEPROM, it is desirable that the resistance of the control gate electrode in the transistor be lower in terms of the suppression of RC delay. Polysilicon doped with impurities and thus having conductivity has been used for the control gate electrode. However, along with increasing demands for a higher velocity in the EEPROM, silicide generally lower in resistance than polysilicon is increasingly used to form the control gate electrode. Silicide is formed by heating a reacting species metal after depositing it on polysilicon, and then causing a reaction between polysilicon and the metal. However, silicide is generally more resistant to an etching gas and a drug solution for dry etching than polysilicon, and is more difficult to process than polysilicon. Therefore, when silicide is used to form the control gate electrode, a control gate film is first formed by polysilicon. Then, polysilicon is processed into a control gate electrode pattern and then silicidated.
Here, a silicon nitride film is generally used as a hard mask for the formation of the control gate electrode pattern. The reason is that a resist for lithography alone is not sufficient as a protective film during processing.
In general, the silicon nitride film used for the processing of the control gate electrode pattern remains unremoved even after the processing of the control gate electrode pattern. Further, after the processing of the control gate electrode pattern, a barrier nitride film for preventing the diffusion of impurities from an insulating film between the control gate electrodes to the cell transistor and the peripheral transistor, and a silicon nitride film serving as a stopper in the processing of contacts are again stacked on the control gate electrode pattern. That is, for the silicidation of the control gate electrode pattern, the silicon nitride film on the control gate electrode pattern has to be once removed to expose polysilicon. The dry etching is generally used to remove the silicon nitride film.
However, a charge (electrons and holes) in plasma attempts to enter the cell transistor and the peripheral transistor during the etching since the dry etching is usually carried out in plasma atmosphere. The silicon nitride film is resistant to the entrance of the charge, but polysilicon is not resistant thereto. Moreover, the silicon nitride film has a certain degree of variation in thickness. Therefore, if the etching is carried out for sufficient time to completely remove the entire silicon nitride film on the control gate electrode pattern, polysilicon is exposed in parts where the silicon nitride film is thin. Exposed polysilicon is subjected to plasma, and the charge enters polysilicon. The charge that has entered is trapped in the interpoly insulating film of the cell transistor and in the gate oxide film of the peripheral transistor, which induces variation of the threshold value corresponding to the trapped charge. This varies the threshold values of the cell transistor and the peripheral transistor, and causes a decrease in the reliability of the EEPROM.
In this manner, the reduction of charge accumulation (charge-up) due to the dry etching is required for the improvement of the reliability of the EEPROM having silicide in the control gate electrode.
In addition, in order to prevent charging damage, there has been already proposed a device having a configuration in which a dummy wiring line that is not used for circuit operation is provided in a MIS transistor formation area having a thick gate insulating film (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 2000-183043). However, this proposal has a problem that the number of manufacturing processes and the area of a device tend to increase.